1. Field of the Invention
The present invention relates to a digital to analog converter (DAC) and a source driver chip thereof, and more particularly, to a digital to analog converter and a source driver chip thereof capable of timely outputting Gamma voltages to a display to avoid abnormal display in many kinds of product applications.
2. Description of the Prior Art
In general, in a source driver chip of a liquid crystal display (LCD), a digital to analog converter may select a proper Gamma voltage from a plurality of Gamma voltages to output to an output stage according to a digital select signal, so as to drive a panel to display with accurate gray scales. In order to avoid continuously utilizing a voltage with a same polarity (e.g. positive polarity or negative polarity) to drive liquid crystal molecules, which reduces polarization or refraction of the liquid crystal molecules such that quality of image display deteriorates, the prior art has disclosed a method of dividing the Gamma voltages to positive Gamma voltages and negative Gamma voltages, to drive the liquid crystal molecules with reversed polarities.
In detail, please refer to FIG. 1, which is a schematic diagram of Gamma voltages. As shown in FIG. 1, a Gamma voltage greater than a middle voltage VDDA/2 is a positive Gamma voltage, which can drive the liquid crystal molecules with a positive polarity; a Gamma voltage less than the middle voltage VDDA/2 is a negative Gamma voltage, which can drive the liquid crystal molecules with a negative polarity, i.e. the middle voltage VDDA/2 is a middle value between a plurality of positive Gamma voltages and a plurality of negative Gamma voltages, wherein different digital select signals DSS are corresponding to different Gamma voltages to cause different gray scales.
In such a situation, please refer to FIG. 2A, which is a schematic diagram of a source driver chip 20. As shown in FIG. 2A, a positive Gamma voltage generator 202 can generate positive Gamma voltages VP[0]˜VP[n] for a p-type digital to analog converter 206 to select one of the positive Gamma voltages VP[0]˜VP[n] as an output voltage VOUTP to an output buffer 210 or 212 according to the digital select signal DSS, to drive the panel to display with specific gray scales. Similarly, a negative Gamma voltage generator 204 can generate negative Gamma voltages VN[0]˜VN[n] for an n-type digital to analog converter 208 to select one of the negative Gamma voltages VN[0]˜VN[n] as an output voltage VOUTN to an output buffer 210 or 212 according to the digital select signal DSS, to drive the panel to display with specific gray scales.
Under this structure, please refer to FIG. 2B and FIG. 2C, which are schematic diagrams of partial circuits of the p-type digital to analog converter 206 and the n-type digital to analog converter 208 in FIG. 2A, respectively. FIG. 2B and FIG. 2C only illustrate circuits related to positive Gamma voltages VP[n−3]˜VP[n] and negative Gamma voltages VN[n−3]˜VN[n] closest to the middle voltage VDDA/2 among the positive Gamma voltages VP[0]˜VP[n] and the negative Gamma voltages VN[0]˜VN[n] in the p-type digital to analog converter 206 and the n-type digital to analog converter 208, to illustrate the structures and operations of the p-type digital to analog converter 206 and the n-type digital to analog converter 208. Among those Gamma voltages, the negative Gamma voltage VN[n] and the positive Gamma voltage VP[n] are closest to the middle voltage VDDA/2.
As shown in FIG. 2B and FIG. 2C, in comparison with other digital to analog converters all utilizing logic gates (transmission gates) as switches for selecting to output the output voltage VOUTP, the source driver chip 20 can utilize a difference between polarities of two transmission paths, to implement p-type transistors as all of the switches for selecting to output the output voltage VOUTP in the p-type digital to analog converters 206, and implement n-type transistors as all of the switches for selecting to output the output voltage VOUTN in the n-type digital to analog converter 208, so as to reduce areas of the digital to analog converters 206 and 208 by half.
In detail, on-resistance of a transistor is negatively related to the overdrive voltage of the transistor. When the overdrive voltage rises, the on-resistance decreases; on the contrary, when the overdrive voltage falls, the on-resistance increases, wherein the overdrive voltage is a difference between the gate-to-source voltage and the threshold voltage of the transistor, i.e. Vgs−Vt. In such a situation, for the p-type digital to analog converter 206 all implemented by p-type transistors as switches, when the input Gamma voltage becomes higher, the gate-to-source voltage becomes higher and the overdrive voltage rises such that on-resistance becomes lower, and hence the p-type digital to analog converter 206 are suitable for selecting and outputting the positive Gamma voltages VP[0]˜VP[n] since the positive Gamma voltages VP[0]˜VP[n] gradually becomes greater than the middle voltage VDDA/2. Similarly, for the n-type digital to analog converter 208 all implemented by n-type transistors as switches, when the input Gamma voltage becomes lower, the gate-to-source voltage becomes higher and the overdrive voltage rises such that on-resistance becomes lower, and hence the n-type digital to analog converter 208 are suitable for selecting and outputting the negative Gamma voltages VN[0]˜VN[n] since the negative Gamma voltages VN[0]˜VN[n] gradually becomes smaller than the middle voltage VDDA/2.
On the other hand, take the p-type digital to analog converter 206 as an example to illustrate the operation of selecting and outputting Gamma voltages. The digital select signal DSS includes select signals SELB[n], SEL[n], SELB[n+1], SEL[n+1], and SELB[n+2]. The select signal SELB[n] may be a binary code. The select signal SEL[n] is an inverse signal of the select signal SELB[n], and the select signal SEL[n+1] is an inverse signal of the select signal SELB[n+1]. In such a condition, the select signals SELB[n] and SEL[n] can control to turn on both the p-type transistors MP1, MP3 or both the p-type transistors MP2, MP4 simultaneously, the select signals SELB[n+1] and SEL[n+1] can control to turn on the p-type transistor MP5 or MP6, and the select signal SELB[n+2] can control whether to turn on the p-type transistor MP7 (since the select signal SELB[n+2] still needs to be utilized for selecting and outputting the positive Gamma voltages VP[n−7]˜VP[n−4]). In such a condition, by utilizing a series of binary codes of the digital select signal DSS for selection control, a transmission path between one of the positive Gamma voltages VP[0]˜VP[n] and the output voltage VOUTP can be conducted as an output path to output the output voltage VOUTP, e.g. to turn on the p-type transistors MP4, MP6, MP7 and the follow-up p-type transistors to form a transmission path P1 between the positive Gamma voltage VP[n] and the output voltage VOUTP.
Similarly, in the n-type digital to analog converter 208, selection control can also be performed with a series of binary codes of the digital select signal DSS, and a transmission path between one of the negative Gamma voltages VN[0]˜VN[n] and the output voltage VOUTN can be conducted as an output path to output the output voltage VOUTN, e.g. to turn on the n-type transistors MN4, MN6, MN7 and the follow-up n-type transistors to form a transmission path N1 between the negative Gamma voltage VN[n] and the output voltage VOUTN. The above operation of performing output selection with a series of binary codes is well-known for those skilled in the art.
However, with the increase of definition, the quantity of transistors in the transmission paths may increase, such that on-resistance of the transmission paths may also increase, and the transmission time becomes longer accordingly. Therefore, in many kinds of product applications with high image updating rate, data can not be transmitted timely, which may cause abnormal display. Take the n-type digital to analog converter 208 as an example, when the quantity of n-type transistors in the transmission path increases, and the negative Gamma voltage increases and the overdrive voltage decreases, e.g. the Gamma voltage VN[n] closest to the middle voltage VDDA/2 and the corresponding transmission path N1, at this moment, on-resistance of each n-type transistor increases, and the quantity of turned-on transistors connected in-serial in the transmission path also increases, such that time constant of the transmission path increases, and thus a signal can not be outputted timely. Similarly, the same problem may appear in the positive Gamma voltage VP[n] closest to the middle voltage VDDA/2 and the corresponding transmission path P1 in the p-type digital to analog converter 206. Thus, there is a need for improvement of the prior art.